Application of HART Protocol in Intelligent Electromagnetic Flowmeter
Smart electromagnetic flow meters compliant with the HART protocol not only feature flow detection and local display capabilities, but also support remote configuration via host computers. They enable users to adjust the flow meter's zero point and measurement range while facilitating self-diagnosis. These features significantly streamline operation and maintenance procedures, thereby enhancing market competitiveness. This paper will analyze technical implementation challenges of HART-based smart electromagnetic flow meters from the perspective of hardware circuit design.
The hardware system circuit of intelligent electromagnetic flowmeter adopts modular design, which mainly includes four parts: sensor module, MCU module, HART communication module and human-machine interface module.
The microcontroller controls the low-frequency excitation current to the sensor's coil while detecting minute electrical signals from the electromagnetic flow sensor. These signals are amplified and then processed by the microcontroller via an analog-to-digital converter (ADC). The microcontroller collects, analyzes, and processes the data, displaying both instantaneous and cumulative flow rates on the LCD screen. Additionally, it performs flow compensation using predefined formulas, with the adjusted signals transmitted to the host computer through a HART communication module for remote control.
1、Design of HART Communication Module
The HT2012 chip is used to handle the demodulation and modulation of communication signals in the HART protocol. The diagram below shows the connection between the modem and the microprocessor.
The demodulation process of the HART signal: The HT2012 chip, connected to the microprocessor, receives pulse signals from the band-pass filter. The chip demodulates these signals, converting the 1200Hz and 2200Hz pulse signals into digital 1s and 0s respectively. The digital signals are then output through the ORXD port of the HT2012 chip. The CPU processes the received data to execute corresponding tasks.
2、HT2012 and External Interfaces
The HART digital signal specification is a sinusoidal AC current signal with a peak of 1mA and an average of 0mA, which is converted into a sinusoidal AC voltage signal through line impedance. In contrast, the HT2012 input and output signals are square wave signals ranging from 0 to 5V. Therefore, a filtering and shaping circuit is required between the HT2012 and the external HART signal.
As shown in the figure, the TLC27-based filter functions as a bandpass filter to reduce noise interference in the received signal. It also eliminates waveform spikes, smoothing out the received signal. The digital square wave circuit formed by TLC37 converts the filtered sine wave into a corresponding square wave, enabling HT2012 to receive it.
In the diagram below, buffer 74HC126 functions to smooth the rising and falling edges of square waves, ensuring the signal meets the HART physical layer specification requirements for signal waveform edges. Smoother edge transitions reduce crosstalk with other networks.
The HT2012 device requires an externally supplied precise 460.8kHz clock signal with strict frequency accuracy requirements of ±0.1%. Directly connecting a standard 460.8kHz crystal oscillator would not only increase system power consumption but also incur higher costs due to the need for custom manufacturing of non-standard components. To address this challenge, the system employs a 1.8432MHz crystal oscillator for clock signal generation. After quadrupling processing through the CD4013 frequency divider, the resulting 1.8432MHz/4=460.8kHz frequency signal perfectly meets the operational requirements of HT2012.
Furthermore, the internal voltage regulator of AD421 works in tandem with the external field-effect transistor DN25D to regulate the input voltage, delivering a stable +3.3V power supply for other devices. The FSK signal transmitted via the HART protocol is coupled through a capacitor and fed into AD421, where it is converted into a corresponding ±0.5mA sinusoidal current signal. This conversion achieves a seamless transition from voltage to current signals, with the resulting current being superimposed within the 4-20mA range and delivered to receiving devices, thereby completing the HART protocol data exchange. In this circuit, the coupling capacitor is meticulously calibrated at 0.0033μF to ensure stable signal transmission.
