HART protocol current output characteristics and application guide
The HART protocol (Open Communication Protocol for Addressable Remote Sensor High-Speed Channels) enables bidirectional 1.2kHz/2.2kHz FSK (Frequency Shift Keying) digital communication within traditional analog 4mA to 20mA current loops. This facilitates sensor/actuator monitoring and demonstrates significant advantages during equipment installation, monitoring, and maintenance processes. While HART provides maintenance personnel with numerous conveniences through portable auxiliary devices for sensor/actuator queries, full utilization of HART's benefits requires connecting sensors/actuators to control systems equipped with HART-compatible current inputs or outputs. This article focuses on HART-supported current inputs and challenges associated with integrating HART functionality into 4mA to 20mA input designs with limited space constraints.
Let's first examine the HART FSK transmitter circuit. Figure 1 illustrates a conventional design of such a circuit. Following its analysis, we will present an optimized version that achieves space and cost savings.
Figure 1. Traditional HART FSK transmission circuit
In Figure 1, Rsense is used to convert 4mA to 20mA signals into 1V to 5V signals readable by the ADC. The HART FSK transmission circuit ac-couples ±500mV HART FSK signals to the 4mA to 20mA loop through capacitor C1. These signals may present either sine wave or trapezoidal waveforms. The HART modem output requires buffers with sufficient driving capability due to Rsense's low impedance and potential high capacitance on current loop cables. When HART signals are inactive, the buffer output exhibits low loop impedance, which could compromise 4mA to 20mA signal transmission. To address this, switch SW1 is connected in series with the buffer output to provide high impedance during inactive periods.
When SW1 is activated, the 4mA to 20mA loop voltage may fluctuate between 1V and 5V. Since these variations are ac-coupled to SW1, the switch's input terminals may experience voltages up to ±4V. To address this, the switch may require a bipolar power supply with ±5V or higher voltage levels, or alternatively opt for a photoelectric switch. A tri-state buffer serves as another viable solution, though it may necessitate a bipolar power supply. Transformer isolation can also be implemented. Considering HART signal frequencies, an audio transformer might be required, but this could result in bulky components and significant PCB space occupation.
Figure 2 demonstrates an improved HART FSK transmission circuit design, which offers advantages in space-saving and cost efficiency. In this circuit, the AD5700 HART modem's driving capability is sufficient to directly drive the ±500mV FSK signal into the current loop without requiring external buffers.
Figure 2. Improved HART FSK transmission circuit
When the modem is not transmitting signals, the FSK output of AD5700 will be biased to 0.75V with an impedance of 70kΩ. Resistors R2 and R3 provide enhanced 0.75V biasing, offering an AC impedance of 1.7kΩ. This 1.7kΩ impedance combined with capacitor C1 forms a high-pass filter that ensures stable output performance even under worst-case input conditions ranging from 4mA to 20mA (±16mA at 25Hz and 200Ω Rsense). This configuration drives the HART modem's FSK output between 0V and 1.5V, enabling the entire system to operate with a single-polarity power supply as low as 1.62V – meeting the minimum supply voltage requirement for HART modems.
Another critical consideration is input impedance, which must exceed 230Ω. To ensure adequate input impedance, the 250Ω input resistor is split into two components: 50Ω and 200Ω. The AC input impedance is calculated as R1+ (Rsense||R2||R3) × 230Ω. If necessary, this impedance can be increased by raising the values of the 0.75 bias resistor (R2 and R3). While adding an additional 50Ω resistor to the FSK transmission path may slightly attenuate the FSK signal, the resulting voltage level still complies with HART specification requirements.
Since the current loop operates in a voltage swing mode, a portion of current will flow through C1, R2, and R3. It is essential to ensure this does not significantly affect the 4mA to 20mA analog signal. An error margin of <0.1% can be considered equivalent to an acceptable contribution of 7 times the time constant (τ). Therefore, 7τ = 7×R×C = 7×(R2||R3)×C1 = 30ms. The 4mA to 20mA analog signal transmission frequency is limited to 25Hz, corresponding to a 40ms cycle period. This value exceeds the 7-fold time constant, meaning additional current measurement errors will consistently remain below 0.1%. The improved circuit design (as shown in Figure 2) eliminates the need for buffers, switches, or bipolar power supplies. These three components significantly reduce system space requirements and costs compared to traditional HART FSK transmission circuits.
The circuit for HART FSK input is shown in Figure 3. This design incorporates a bandpass filter that suppresses low-frequency analog signal transmission while remaining unaffected by higher-frequency interference. The filter configuration is specifically tailored for the AD5700 sensor and may vary depending on the HART modem model. A key feature of this bandpass filter is the 150kΩ input impedance provided by resistor R1, which significantly enhances resistance to transient noise interference.
Figure 3. HART FSK input
The current measurement circuit for 4mA to 20mA ranges is illustrated in Figure 4. A 200Ω precision Rsense resistor converts the 4mA-to-20mA signal into a 0.8V-to-4V voltage signal, which is then processed by an ADC. The signal passes through a bipolar low-pass filter (R2, C1, R3, C2) to suppress HART FSK interference before being fed into the ADC for conversion.
Figure 4. Current measurement circuit
The circuit described herein has been successfully constructed and tested, serving as a reference circuit for PLC/DCS four-channel voltage and current inputs while maintaining compatibility with HART (CN0364). The described circuit can be fully implemented on this circuit board, which also supports HART multiplexing across four input channels. During channel testing, the FSK transmission switch remains either on or off; when kept on, the circuit configuration remains identical to that shown in Figure 2.
This paper outlines the implementation of hardware on HART-compatible analog inputs. Additionally, it demonstrates an enhanced HART FSK transmission circuit utilizing the AD5700 HART modem. The improved design eliminates the need for external buffers or switches, while optimizing PCB space utilization and reducing costs. Furthermore, the circuit requires no bipolar power supply, which not only saves space and reduces expenses but also simplifies power management complexity.